/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_RC8088_LOADCFG_H__
#define __HAL_RC8088_LOADCFG_H__

#include <stdio.h>
#include <string.h>
#include "hal_rc8088.h"

#define INPUT_CLK_FREQ          (40)  //40M   54M
#define ADC_N_NUM               (8)
#define PLL1_N_NUM              (19)  //19    14
#define FREF_N_NUM              (19)
#define ADC_CLK_FREF            (INPUT_CLK_FREQ*PLL1_N_NUM*ADC_N_NUM*2.0)
#define PLL2_FREF               (ADC_CLK_FREF/2.0/FREF_N_NUM)
//#define CPPLL_FREF              (78.0*1000.0/12.0/PLL2_FREF)

typedef struct{
	uint32_t waveCfg0;
	uint32_t waveCfg1;
	uint32_t waveCfg2;
	uint32_t powerCfg0;
	uint32_t powerCfg1;
	uint32_t anaCfg0;
	uint32_t anaCfg1;
	uint32_t anaCfg2;
	uint32_t anaCfg3;
	uint32_t anaCfg4;
	uint32_t anaCfg5;
	uint32_t lutRampCfg0;
	uint32_t lutRampCfg1;
	uint32_t lutRampCfg2;
	uint32_t lutRampCfg3;
	uint32_t lutRampCfg4;
	uint32_t lutRampCfg5;
	uint32_t lutRampCfg6;
	uint32_t lutRampCfg7;
	uint32_t lutStartFreqCfg0;
	uint32_t lutStartFreqCfg1;
	uint32_t lutStartFreqCfg2;
	uint32_t lutStartFreqCfg3;
	uint32_t lutAdcRmaCfg0;
	uint32_t lutAdcRmaCfg1;
	uint32_t lutAdcRmaCfg2;
	uint32_t lutTxEnCfg0;
	uint32_t lutTxEnCfg1;
	uint32_t lutBpmCfg0;
	uint32_t lutBpmCfg1;
	uint32_t lutTx0PhaseCfg0;
	uint32_t lutTx0PhaseCfg1;
	uint32_t lutTx1PhaseCfg0;
	uint32_t lutTx1PhaseCfg1;
	uint32_t lutTx2PhaseCfg0;
	uint32_t lutTx2PhaseCfg1;
	uint32_t lutTx3PhaseCfg0;
	uint32_t lutTx3PhaseCfg1;
	uint32_t lutTx4PhaseCfg0;
	uint32_t lutTx4PhaseCfg1;
	uint32_t lutTx5PhaseCfg0;
	uint32_t lutTx5PhaseCfg1;
	uint32_t lutTx6PhaseCfg0;
	uint32_t lutTx6PhaseCfg1;
	uint32_t lutTx7PhaseCfg0;
	uint32_t lutTx7PhaseCfg1;
  uint32_t RFU[2];
}STRUCT_PROFILELUT;
typedef struct{
	uint32_t profileAddr;
	uint32_t rampMemAddr;
	uint32_t startFreqMemAddr;
	uint32_t adcRmaMemAddr;
	uint32_t txEnMemAddr;
	uint32_t bpmMemAddr;
	uint32_t tx0PhaseMemAddr;
	uint32_t tx1PhaseMemAddr;
	uint32_t tx2PhaseMemAddr;
	uint32_t tx3PhaseMemAddr;
	uint32_t tx4PhaseMemAddr;
	uint32_t tx5PhaseMemAddr;
	uint32_t tx6PhaseMemAddr;
	uint32_t tx7PhaseMemAddr;
	uint32_t testMemAddr;
}STRUCT_PROFILEMEM_ADDR;
typedef struct{
	//CFG0
	uint32_t cfg0_UFT0;
	uint32_t enmipi;
	uint32_t enadc;
	uint32_t enlorx;
	uint32_t enrxrf;
	uint32_t enrxbb;
	uint32_t enlotx;
	uint32_t enlofan;
	uint32_t enpll;
	//CFG1
	uint32_t ct_acccur;
	uint32_t cfg1_UFT0;
	uint32_t ct_vcoband;
	uint32_t cfg1_UFT1;
	uint32_t envco;
	//CFG2
	uint32_t cfg2_NC;
	uint32_t cfg2_UFT0;
	uint32_t SYNC_source;
	uint32_t CLK40M_source;
	uint32_t RXBBTSTsigFreq;
	uint32_t RXBBTSTsig;
	uint32_t GPADC3;
	uint32_t cfg2_UFT1;
	uint32_t GPADC2;
	uint32_t cfg2_UFT2;
	uint32_t GPADC1;
	uint32_t cfg2_UFT3;
	//CFG3
	uint32_t cfg3_UFT0;
	uint32_t TX8PowerManual;
	uint32_t TX7PowerManual;
	uint32_t TX6PowerManual;
	uint32_t TX5PowerManual;
	uint32_t TX4PowerManual;
	uint32_t TX3PowerManual;
	uint32_t TX2PowerManual;
	uint32_t TX1PowerManual;
	//CFG4
	uint32_t TX8PowerAdj;
	uint32_t TX7PowerAdj;
	uint32_t TX6PowerAdj;
	uint32_t TX5PowerAdj;
	uint32_t TX4PowerAdj;
	uint32_t TX3PowerAdj;
	uint32_t TX2PowerAdj;
	uint32_t TX1PowerAdj;
	//CFG5
	uint32_t cfg5_UFT0;
	uint32_t HPsta1;
	uint32_t HPsta2;
	uint32_t cfg5_UFT1;
	uint32_t Gainsta1;
	uint32_t Gainsta2;
	uint32_t Gainsta3;
	//CFG6
	uint32_t cfg6_UFT0;
	//CFG7
	uint32_t cfg7_UFT0;
	//CFG8
	uint32_t cfg8_UFT0;
	//CFG9
	uint32_t cfg9_UFT0;
	uint32_t losel;
	uint32_t cfg9_UFT1;
	//CFG10
	uint32_t cfg10_UFT0;
	//CFG11
	uint32_t cfg11_UFT0;
	//CFG12
	uint32_t cfg12_UFT0;
	//CFG13
	uint32_t cfg13_UFT0;
	//CFG14
	uint32_t cfg14_UFT0;
	//CFG15
	uint32_t cfg15_UFT0;
	uint32_t RX_Gain0;
	uint32_t cfg15_UFT1;
	//CFG16
	uint32_t cfg16_UFT0;
	//CFG17
	uint32_t cfg17_UFT0;
	//CFG18
	uint32_t cfg18_UFT0;
	//CFG19
	uint32_t cfg19_UFT0;
	//CFG20
	uint32_t MIPI_rate_postDiv;
	uint32_t cfg20_UFT0;
	uint32_t MIPI_rate_mDiv;
	uint32_t cfg20_UFT1;
	uint32_t MIPI_rate_fractionDiv;
	uint32_t cfg20_UFT2;
	//CFG21
	uint32_t cfg21_UFT0;
	//CFG22
	uint32_t mipidphy_cfg0_ch3;
	uint32_t mipidphy_cfg0_ch2;
	uint32_t mipidphy_cfg0_ch1;
	uint32_t mipidphy_cfg0_ch0;
	//CFG23
	uint32_t mipidphy_cfg0_ch7;
	uint32_t mipidphy_cfg0_ch6;
	uint32_t mipidphy_cfg0_ch5;
	uint32_t mipidphy_cfg0_ch4;	
	//CFG24
	uint32_t mipidphy_cfg0;
	uint32_t mipidphy_cfg0_chck2;
	uint32_t mipidphy_cfg0_chck;
	//CFG25
	uint32_t cfg25_UFT0;
}STRUCT_USERCFG_ANALOG;
typedef struct{
	uint32_t gpio_sta;
	uint32_t gpio_oe;
	uint32_t clk_out_mode;
	uint32_t adc_dmux;
	uint32_t dclk_div;
}STRUCT_USERCFG_COMMON;
typedef struct{
	//cfg0
	uint32_t samp_pt_rsfb;	
	uint32_t samp_pt_fac;	
	uint32_t samp_pt;
	//cfg1
	uint32_t rx_num;
	uint32_t pp_num;
	uint32_t chirp_rma;
	uint32_t chirp_num;
	//cfg2
	uint32_t cic_sec;
	uint32_t down_fac;
	uint32_t adc_lsb;
	uint32_t adc_cat_mode;
	uint32_t adc_test_mode;
	uint32_t adc_dsize;
	uint32_t adc_clk_mode;
	//cfg3
	uint32_t rx_antseq7;
	uint32_t rx_antseq6;
	uint32_t rx_antseq5;
	uint32_t rx_antseq4;
	uint32_t rx_antseq3;
	uint32_t rx_antseq2;
	uint32_t rx_antseq1;
	uint32_t rx_antseq0;
	//cfg4
	uint32_t cq1_pt_rsfb;
	uint32_t cq1_pt_fac;
	uint32_t cq2_timing_limit;
	//cfg5
	uint32_t cq12_ch_num;
	uint32_t cq_pt_num;
	uint32_t cq_sec_num;
}STRUCT_USERCFG_PREP;
typedef struct{
	//cfg0
	uint32_t sw_timing_mode;
	uint32_t sw_diff_mode;
	uint32_t valid_ch_num;
	uint32_t timing_mul_fac;
	uint32_t diff_mul_fac;
	uint32_t dc_removal;
	uint32_t zo_diff_mode;
	uint32_t zo_mode;
	uint32_t zo_zero_len;
	//cfg1
	uint32_t sw_timing_thres;
	uint32_t sw_diff_thres;
}STRUCT_USERCFG_P10;
typedef struct{
	//cfg0
	uint32_t trans_mode;
	uint32_t interCnt;
	uint32_t burst_len;
	uint32_t prep2rd_dly;
	uint32_t wr2mipi_dly;
	uint32_t entry_e_en;
	uint32_t entry_d_en;
	uint32_t entry_c_en;
	uint32_t entry_b_en;
	uint32_t entry_a_en;
	//cfg1
	uint32_t d_ch_num;
	uint32_t d_intraCnt;
	uint32_t c_intraCnt;
	uint32_t b_intraCnt;
	//cfg2
	uint32_t e_intraCnt;
	//cfg3
	uint32_t e_jumpCnt;
	uint32_t e_baseAddr;
}STRUCT_USERCFG_DMA;
typedef struct{
	//cfg0
	uint32_t win_sym;
	uint32_t win_en;
	uint32_t out_mode;
	uint32_t out_exp;
	uint32_t fftPt;
	uint32_t mode;
	//cfg1
	uint32_t outLsfEn;
	uint32_t outSfb;
	uint32_t winLsfb;
}STRUCT_USERCFG_FFT;
typedef struct{
	//cfg0
	uint32_t mipi_crc_en;
	uint32_t mipi_64bit_mode;
	uint32_t mipi1_en;
	uint32_t mipi0_en;
	uint32_t mipi_dlane_mode;
	uint32_t mipi_data_type;
	uint32_t mipi_wlevel;
	//cfg1
	uint32_t mipi_chirp_num;
	uint32_t mipi_payload_len;
	//cfg2
	uint32_t mipi_head_cfg_en;
	uint32_t mipi_sf_head;
	//cfg3
	uint32_t mipi_ef_head;
	uint32_t mipi_sl_head;
	uint32_t mipi_el_head;
	uint32_t mipi_lp_head;
	//cfg4
	uint32_t mipi_tck_pre;
	uint32_t mipi_tck_zero;
	uint32_t mipi_tck_post;
	uint32_t mipi_tck_trail;
	uint32_t mipi_tlpx;
	uint32_t mipi_ths_zero;
	uint32_t mipi_ths_trail;
}STRUCT_USERCFG_MIPI;
typedef struct{
	//cfg0
	uint32_t sf0_profileLoopInf;
	uint32_t sf0_profileLoopNum;
	uint32_t sf0_profileNumA;
	uint32_t sf0_profileNumB;
	uint32_t sf0_interFrameIdleTimeScaleB;
	uint32_t sf0_interFrameIdleTimeValueB;
	//cfg1
	uint32_t sf1_valid;
	uint32_t sf1_profileLoopInf;
	uint32_t sf1_profileLoopNum;
	uint32_t sf1_profileNumA;
	uint32_t sf1_profileNumB;
	uint32_t sf1_interFrameIdleTimeScaleB;
	uint32_t sf1_interFrameIdleTimeValueB;
	//cfg2
	uint32_t sf2_valid;
	uint32_t sf2_profileLoopInf;
	uint32_t sf2_profileLoopNum;
	uint32_t sf2_profileNumA;
	uint32_t sf2_profileNumB;
	uint32_t sf2_interFrameIdleTimeScaleB;
	uint32_t sf2_interFrameIdleTimeValueB;
	//cfg3
	uint32_t sf3_valid;
	uint32_t sf3_profileLoopInf;
	uint32_t sf3_profileLoopNum;
	uint32_t sf3_profileNumA;
	uint32_t sf3_profileNumB;
	uint32_t sf3_interFrameIdleTimeScaleB;
	uint32_t sf3_interFrameIdleTimeValueB;
}STRUCT_USERCFG_SF;
typedef struct{
	//cfg0
	uint32_t profile_man_vld;
	//cfg1
	uint32_t ramp_a_inc;
	uint32_t ramp_a_time;
	//cfg2
	uint32_t ramp_b_inc;
	uint32_t ramp_b_time;
	//cfg3
	uint32_t ramp_c_inc;
	uint32_t ramp_c_time;
	//cfg4
	uint32_t startFreq;
	//cfg5
	uint32_t adcRma;
	uint32_t txEn;
	//cfg6
	uint32_t tx0Phase;
	uint32_t tx1Phase;
	uint32_t tx2Phase;
	uint32_t tx3Phase;
	//cfg7
	uint32_t tx4Phase;
	uint32_t tx5Phase;
	uint32_t tx6Phase;
	uint32_t tx7Phase;
	//cfg8
	uint32_t ramp_sycn_maskA;
	uint32_t ramp_sycn_maskB;
	uint32_t ramp_sycn_maskC;
	uint32_t pll_acc_maskA;
	uint32_t pll_acc_maskB;
	uint32_t pll_acc_maskC;
	uint32_t pa_en_maskA;
	uint32_t pa_en_maskB;
	uint32_t pa_en_maskC;
	uint32_t loopInf;
	uint32_t loopNum;
}STRUCT_USERCFG_PROFMAN;
typedef struct{
	RC8088_MemDat_st *txpBuf_Addr;
	RC8088_MemDat_st *cBuf_Addr;
}STRUCT_USERCFG_MEMADDR;

typedef struct{
    int Enable;
    int DlaneMode;
    int LaneSpeed;
    int DataType;
    int DelayCK[2];
    int DelayCH[8];
    int TckPre;
    int TckZero;
    int TckPost;
    int TckTrail;
    int Tlpx;
    int ThsZero;
    int ThsTrail;
}STRUCT_MIPICFG;
typedef struct{
	float freqStart;
	float bandwidth;
	float sweepTimeA;
	float sweepTimeB;
	float sweepTimeC;
	int numChirp;
	int numRma;
	int txPhase[8];
	int txEn;
}STRUCT_BASIC;
typedef struct{
	//basicWave
	STRUCT_BASIC basicCfg;
	//advanceWave
	STRUCT_USERCFG_SF userSF;
	float advFreqStart;
	float advFreqStop;
	//common
	int numFrame;
	int downFac;
	int numPT;
	int numPrepChirp;
	int cic_sec;
	int numRX;
	int rxAntSeq[8];
	int txAntPower;
	int rxAntGain0;
	int rxAntGain1;
	int rxAntGain2;
	int rxAntGain3;
	int HPF0;
	int HPF1;
	STRUCT_MIPICFG mipiCfg;
	int fftEn;
	int fftWinEn;
	int fftOutMode;
	int fftNumPT;
	int cpEn;
	int cqEn;
	int dataEn;
	int zero_out_bypass;
	int numCqPT;
	int dc_removal;
	int win_sym;
	float cq2_limit;
//	int numEdma;
	int adc_dsize;
	int numMipiChirp;
//	int numMipi;

	// lock cfg
	STRUCT_USERCFG_ANALOG userAnalog;
	STRUCT_USERCFG_COMMON userCommon;
	STRUCT_USERCFG_PREP userPrep;
	STRUCT_USERCFG_P10 userP10;
	STRUCT_USERCFG_DMA userDMA;
	STRUCT_USERCFG_FFT userFFT;
	STRUCT_USERCFG_MIPI userMipi;

	STRUCT_USERCFG_PROFMAN userProfMan;
	STRUCT_USERCFG_MEMADDR userMemAddr;
} STRUCT_RC8088_USERCFG;

void HAL_RC8088_userCfgLock(STRUCT_RC8088_USERCFG *rc8088_userCfg);
uint32_t HAL_RC8088_CalcStartFreqReg(double startFreq);
uint32_t HAL_RC8088_CalcRampReg(double bandwidth,double rampTime);
uint32_t HAL_RC8088_CalcMipiRate(STRUCT_RC8088_USERCFG *rc8088_userCfg);
uint32_t HAL_RC8088_RegLoadConfig(RC8088_RWCfg_st *pCfg,RC8088_RegCfg_st *rc8088_regCfg,STRUCT_PROFILEMEM_ADDR *profileMemAddr,STRUCT_RC8088_USERCFG *rc8088_userCfg);

uint32_t HAL_RC8088_ReadCfg(RC8088_RWCfg_st *pCfg,RC8088_RegCfg_st *rc8088_regCfg);
#endif /*__HAL_RC8088_LOADCFG_H__ */

/************************ (C) COPYRIGHT  *****END OF FILE****/




#define  AS sizeof(STRUCT_USERCFG_MEMADDR)


















